1. Field of the Invention
The present invention relates to a high voltage tolerance circuit, and more particularly, to a high voltage tolerance circuit for programming operation, latch-up test, and ESD protection.
2. Description of the Prior Art
A traditional semiconductor I/O circuit commonly comprises a “pull-up” device and a “pull-down” device. The term “pull-up” device refers to the circuitry adapted to pull an output node to a desirable logical high voltage, e.g. 3.3 volts or 5 volts, whereas the term “pull-down” device refers to the circuitry adapted to pull an output node to a desirable logical low voltage, e.g. 0 voltages.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a driving circuit 10 according to the prior art. The driving circuit 10 comprises a P-type MOS pull-up transistor MP and an N-type MOS pull-down transistor MN. The P-type MOS pull-up transistor is typically formed in an N-well to facilitate the use of CMOS technology in forming N-type MOS pull-down transistors for an I/O pad 12. However, as a result of the P-type MOS pull-up transistor MP being formed in an N-well, when the I/O pad 12 receives an input signal having a voltage that sufficiently exceeds a voltage of a power supply Vs, current may be drawn through the P-type MOS pull-up transistor MP to the power supply. Thus, the driving circuit 10 is not suitable for a high voltage input, such as programming operation.